In modern integrated circuits, gate arrays comprising p-channel field effect transistors (PFETs) and n-channel field effect transistors (NFETs) can be susceptible to latchup. Latch-up causes Metal-Oxide-Silicon FETs (MOSFETs) to consume large amounts of current overheating and destroying the integrated circuit in which latchup occurs. Existing methods for reducing this propensity to complementary MOS (CMOS) latchup have become increasingly less effective as doping levels of the substrates of integrated circuits have decreased. Therefore there is a need in the industry for more robust latchup preventive structures and methods for preventing latchup for gate arrays in integrated circuit chips.